In integrated circuits, large numbers of structures typically must be interconnected, and interconnect conductors use up a significant portion of the surface area of the semiconductor chip. Typically, these conductors are formed as thin films of conductor deposited on insulating materials on the semiconductor surface and defined as lines photolithographically. Efforts to shrink the conductors are limited since line widths can be no smaller than the minimum photolithographically defined line. The cost of decreasing the photolithographic minimum dimension is high, and each such effort has defined succeeding generations of semiconductor products.
In particular, the photolithographically defined interconnect between the node diffusion and trench capacitor of a DRAM cell has posed problems in several generations of DRAM products. This strap must provide a reliable connection with acceptable resistance in a small area.
One approach to avoid the photolithographic limit is the conductive sidewall rail. The width of such rails is determined by the thickness of the deposited conductor, and this thickness can be significantly less than a minimum photolithographic dimension. Articles by C. G. Jambotkar in the IBM Technical Disclosure Bulletin Vol. 25, No. 9, Feb. 1983, p 4785 (Jambotkar) and by H. S. Bhatia, et al in the IBM Technical Disclosure Bulletin Vol. 26, No. 2, July 1983, p 623 (Bhatia) disclose polysilicon resistor rails formed by deposition and directional etch along sidewalls of a window etched in an insulator. In Jambotkar, the rails are formed on insulator. In Bhatia, two ends of the rail are deposited directly on single crystal silicon to form a sidewall connection between two doped regions. A problem arises in Bhatia's process in that exposed silicon adjacent the rails would be attacked during the directional etching of polysilicon to form the rails. Particularly if the single crystal comprises thin doped regions, the damage could degrade device and chip performance.
Commonly assigned U.S. Pat. No. 4,785,337 ("the '337 patent"), issued to D. M. Kenney, (FIG. 9a) does not address this problem with respect to contact between a conductive sidewall rail strap and a node diffusion. The '337 patent and commonly assigned U.S. Pat. No. 5,365,097 issued to D. M. Kenney, (FIG. 13b) also illustrate a second contact between the conductive sidewall rail and another conductor, the contact being along the inner surface of the rail, that is the surface of the rail along the sidewall and most protected from the directional etch.
Thus, a structure and means to form conductive sidewalls is needed that avoids significant attack on exposed doped regions.